1. Field of the Invention
The present invention relates to a thin film transistor panel (hereinafter called "TFT panel") which is used in an active matrix liquid crystal display (LCD) device.
2. Description of the Related Art
An active matrix LCD device, which has thin film transistors (TFTs) as active elements, comprises a TFT panel having a transparent substrate, a plurality of pixel electrodes formed in a matrix form on the transparent substrate, a plurality of gate lines, a plurality of data lines and a plurality of TFTs associated with the individual pixel electrodes; an opposite panel having a transparent substrate and opposite electrodes formed on the transparent substrate and opposite to the pixel electrodes; and a liquid crystal sealed between the TFT panel and the opposite panel. In a color LCD device which provides a color image display, etc., red, green and blue color filters are provided on the opposite panel or the TFT panel in association with the individual pixel electrodes.
There are two layout patterns of the pixels in the active matrix LCD device: (1) mosaic layout pattern in which the pixels are arranged linearly in the row direction and in a zigzag form in the column direction, and (2) grid or matrix layout pattern in which the pixels are arranged linearly both in the row and column directions.
FIGS. 9 and 10 illustrate the structure of a TFT panel used in an LCD device which has pixels arranged in a mosaic pattern. FIG. 9 is a plan view of a part of the TFT panel, and FIG. 10 is an enlarged cross-sectional view taken along the line 10--10 in FIG. 9. This TFT panel is used in a color LCD device which has red, green and blue color filters provided on the opposite panel.
The illustrated TFT panel comprises a transparent substrate 1 made of glass or the like, a plurality of pixel electrodes 2 (2R, 2G, 2B) formed in a matrix form on the transparent substrate 1, a plurality of gate lines Lg, a plurality of data lines Ld provided for respective rows of the pixel electrodes 2 each row for displaying the pixels of the same color, and a plurality of TFTs 3 associated with the individual pixel electrodes 2.
The pixel electrodes 2 are formed by a transparent conductive film, such as an ITO (Indium Tin Oxide) film. The pixel electrodes 2 include pixel electrodes 2R for displaying red pixels (the electrodes facing the red color filter on the opposite panel), pixel electrodes 2G for displaying green pixels (the electrodes facing the green color filter on the opposite panel) and pixel electrodes 2B for displaying blue pixels (the electrodes facing the blue color filter on the opposite panel). The pixel electrodes 2R, 2G and 2B are alternately arranged in the row direction (horizontal direction in FIG. 9). The pixel electrodes 2 are arranged in a zigzag form in the column direction (vertical direction in FIG. 9) in such a manner that groups of the pixel electrodes which display the pixels of the same color are alternately shifted by about 1.5 pitches in the row direction.
As shown in FIG. 10, the TFT 3 comprises a gate electrode GE formed on the substrate 1, a gate insulating film 4, an i-type semiconductor film 5, an n-type semiconductor film 6, a source electrode SE and a drain electrode DE, the latter two electrodes SE and DE being electrically connected via the n-type semiconductor film 6 to the i-type semiconductor film 5.
The gate lines Lg are laid on the substrate 1 along the individual rows in the matrix of the pixel electrodes 2. The gate electrodes of the TFTs 3 in each row and the associated gate line Lg are formed integrally.
The gate insulating film 4 of the TFT 3 is formed on substantially the entire surface of the substrate 1, covering the gate line Lg. The pixel electrode 2 is formed on this gate insulating film 4.
Each gate line Lg is laid facing the edge portion of the previous or next row of the pixel electrodes 2 to the associated row of the pixel electrodes 2. A compensation capacitor for holding the potential of each pixel electrode 2 during the unselected period is constituted by the pixel electrode 2, the gate line Lg and the gate insulating film 4 therebetween.
The data line Ld is laid on a protective insulating film 7 which is formed covering each TFT 3.
The layout pattern of the data lines Ld will be discussed now with reference to the one associated with the green pixel electrodes 2G. The data line Ld runs in a zigzag form along the right-hand edges of the pixel electrodes 2G which are shifted leftward in FIG. 9 and the left-hand edges of the pixel electrodes 2G which are shifted rightward.
The zigzag layout of the data line Ld is employed to shorten its portion between rows of the pixel electrodes 2 (the line extending horizontally in the diagram).
With the data lines Ld laid out as shown in FIG. 9, the position of the data line Ld associated with the TFTs 3 connected to the pixel electrodes 2G shifted leftward is opposite to the position of the data line Ld associated with the TFTs 3 connected to the pixel electrodes 2G shifted rightward. In this TFT panel, therefore, the positional relation between the source electrodes SE and the drain electrodes DE of the TFTs 3 connected to the pixel electrodes 2G shifted leftward is set opposite to the positional relation between the source electrodes SE and the drain electrodes DE of the TFTs 3 connected to the pixel electrodes 2G shifted rightward. This design always allows the source electrode SE of each TFT 3 to be connected to the associated pixel electrode 2G and the drain electrode DE to be connected to the associated data line Ld.
The data line Ld associated with the red pixel electrodes 2R and the data line Ld associated with the blue pixel electrodes 2B are likewise laid out in the same manner as the data line Ld associated with the green pixel electrodes 2G. With regard to the TFTs 3 associated with the pixel electrodes 2R and the pixel electrodes 2B, the positional relation between the source electrodes SE and the drain electrodes DE of the TFTs 3 associated with the pixel electrodes 2 shifted leftward is set opposite to the positional relation between the source electrodes SE and the drain electrodes DE of the TFTs 3 associated with the pixel electrodes 2 shifted rightward.
Each pixel electrode 2 is connected to the source electrode SE of the associated TFT 3 at the extending portion (connecting portion) formed at the edge portion of the electrode 2. Each data line Ld is connected to the drain electrodes DE of the TFTs 3 via contact holes formed in the protective insulating film 7.
The TFT panel used in an LCD device which has pixel electrodes arranged in a grid pattern will now be described. FIG. 11 is a plan view of a part of a conventional TFT panel used in this type of LCD device. This TFT panel is also used in a color LCD device which has the color filters provided on the opposite panel.
The pixel electrodes 2 of different colors of the TFT panel are alternately and linearly arranged in the row direction, while the pixel electrodes 2 for displaying the pixels of the same color are arranged linearly in the column direction. Each data line Ld is linearly laid out along the associated column of the pixel electrodes 2.
In this TFT panel, the positions of the TFTs 3 with respect to the pixel electrodes 2 and the associated data line Ld are the same for every pixel electrode 2. Every TFT 3 therefore has the same positional relationship between the source electrode SE and the drain electrode DE.
This TFT panel has a capacitor line Lc formed facing an associated row of the pixel electrodes 2 on the substrate 1. The compensation capacitor for holding the potential of each pixel electrode 2 is constituted by the pixel electrode 2, the capacitor line Lc and the gate insulating film 4 therebetween.
The pixel electrodes 2, a plurality of films constituting each TFT 3, the gate line Lg, the data line Ld, etc. are generally formed by photolithography. According to the photolithography, a photoresist film is formed on a layer to be patterned, this photoresist film is exposed, the exposed photoresist film is developed to form an etching mask and the layer to be patterned is etched using this etching mask, thereby yielding the desired pattern.
The exposure of the photoresist film is executed by optically reducing a mask pattern, which has enlarged shapes (pattern) of elements to be formed and is formed on an exposure mask, and projecting the mask pattern on the photoresist film.
In the case of manufacturing large TFT panels used in an LCD device with a large screen, it is difficult to perform exposure on the entire substrate at a high precision. In this respect, the production of large TFT panels employs divisional exposure to sequentially expose a plurality of areas on the substrate using a stepper.
If the divisional exposure scheme is used to manufacture the conventional TFT panels, however, the value of the gate-source capacitance of the TFT 3 differs exposure area by exposure area due to the positional misalignment at the time of exposure. Accordingly, the voltage holding characteristic of each pixel of the LCD device differs exposure area by exposure area, causing display blurring.
This problem will now be explained specifically. To begin with, the voltage holding characteristic of each pixel of the LCD device will be discussed with reference to FIG. 12, which is an equivalent circuit diagram of one pixel of the LCD device.
In FIG. 12, "Cgd" denotes a gate-drain capacitor (capacitor between the facing portions of the gate electrode and drain electrode), "Cgs" denotes a gate-source capacitor (capacitor between the facing portions of the gate electrode and source electrode), "Cs" denotes a compensation capacitor (capacitor between the facing portions of the pixel electrode and the gate line or capacitor line), and "C.sub.LC " denotes a capacitor (pixel capacitor) constituted by the pixel electrode, the associated opposite electrode of the opposite panel and the liquid crystal therebetween.
During the selected period of a pixel, a gate pulse is applied to the gate line Lg associated with this pixel, turning on the associated TFT 3. A data signal is applied to the pixel electrode 2 via the enabled TFT 3 from the data line Ld. The voltage between the pixel electrode 2 and the opposite electrode increases along the rising curve according to the voltage-current characteristic of the TFT 3.
In the unselected period of this pixel, the gate pulse is disabled to turn off the TFT 3, causing the voltage between the pixel electrode 2 and the opposite electrode to fall by .DELTA.V from the voltage at the end of the selected period due to the influence of the gate pulse. The decreased voltage becomes the voltage the pixel holds during the unselected period.
The voltage drop .DELTA.V is expressed by an equation (1). EQU .DELTA.V=Vg.multidot.Cgs/(C.sub.LC +Cs+Cgs) (1)
where Vg is the voltage of the gate pulse applied to the gate electrode of the TFT during the selected period.
A description will now be given of the point that the voltage holding characteristic of each pixel of the LCD device differs exposure area by exposure area.
Of the capacitances C.sub.LC, Cs and Cgs which determine the voltage drop .DELTA.V, the pixel capacitance C.sub.LC is the same for all the pixels because every pixel electrode 2 has the same area.
The compensation capacitance Cs is determined by the facing area between the pixel electrode 2 and the gateline Lg or the capacitor line Lc.
Since the gate line Lg is straight in the TFT panel shown in FIG. 9, the area of the gate line Lg facing the pixel electrode 2 does not vary even if the gate line Lg is shifted in the lengthwise direction.
The TFT panel shown in FIG. 11 has two projections which protrude from the capacitor line Lc and face both edge portions of the pixel electrode 2. If the two projections have the same length, even when the capacitor line Lc is shifted in the lengthwise direction to reduce the facing area between one projection and the pixel electrode 2, the facing area between the other projection and the pixel electrode 2 increases accordingly. As a result, the facing area between the capacitor line Lc and the pixel electrode 2 does not vary. In both structures shown in FIGS. 9 and 11, even if the exposure position is shifted in the row direction in the matrix of the pixel electrodes 2, the compensation capacitance Cs is the same for all the pixels.
The gate-source capacitance Cgs is determined by the facing area between the gate electrode GE and the source electrode SE. This facing area changes when the position of the source electrode SE is shifted in the row direction of the pixel electrodes 2 (the lengthwise direction of the gate line Lg or the widthwise direction of the gate electrode GE).
This point will be described specifically with reference to FIGS. 13A and 13B.
FIG. 13A shows the source electrode SE and the drain electrode DE shifted leftward from the reference positions, and FIG. 13B shows the source electrode SE and the drain electrode DE shifted rightward from the reference positions.
As shown in FIG. 13A, if the source electrode SE and the drain electrode DE are formed shifted leftward from the reference positions, the facing area between the gate electrode GE and source electrode SE of the TFT 3 (the hatched area in the diagram) becomes smaller, thus reducing the gate-source capacitance Cgs. If the source electrode SE and the drain electrode DE are formed shifted rightward from the reference positions, on the other hand, the facing area between the gate electrode GE and source electrode SE becomes larger, thus increasing the gate-source capacitance Cgs.
When the TFT panel is produced using the divisional exposure, the error of the misalignment of the exposure mask differs exposure area by exposure area. Therefore, the source electrode SE is formed shifted leftward in one exposure area as shown in FIG. 13A and the source electrode SE is formed shifted rightward in another exposure area as shown in FIG. 13B. The amount of shifting also differs exposure area by exposure area. Accordingly, the gate-source capacitance Cgs of each TFT 3 differs exposure area by exposure area.
If the gate-source capacitance Cgs of each TFT 3 differs exposure area by exposure area, the change in voltage .DELTA.V given from the equation (1) differs exposure area by exposure area. Therefore, the voltage holding characteristic of each pixel in a single LCD device differs exposure area by exposure area, causing display blurring.
If forming positions of the source electrode SE and the drain electrode DE are shifted rightward or leftward from the reference positions, the facing area between the gate electrode GE and source electrode SE changes. As a result, the gate-drain capacitance Cgd of the TFT 3 differs exposure area by exposure area. This does not however raise significant problems because the gate-drain capacitance Cgd does not affect the voltage holding characteristic of the pixel.
In the TFT panel shown in FIG. 9, the positional relation between the source electrode SE and the drain electrode DE of the TFT 3 is reversed row by row. Even in one exposure area, therefore, the gate-source capacitance Cgs differs row by row.
This point will be described with reference to FIGS. 14A and 14B.
FIGS. 14A and 14B illustrate the source electrodes SE and drain electrodes DE of the TFTs 3 in two adjoining rows of the conventional TFT panel shown in FIG. 9 shifted leftward from the reference positions. FIG. 14A shows the TFT 3 whose source electrode SE is located on the left side, and FIG. 14B shows the TFT 3 whose source electrode SE is located on the right side.
If the source electrode SE and drain electrode DE are shifted, for example, leftward as shown in FIGS. 14A and 14B, the facing area between the gate electrode GE and the source electrode SE becomes smaller in the TFT 3 in FIG. 14A, reducing the gate-source capacitance Cgs. In the TFT 3 in FIG. 14B, the facing area between the gate electrode GE and the source electrode SE becomes larger, increasing the gate-source capacitance Cgs.
If the source electrode SE and drain electrode DE are shifted rightward, the facing area between the gate electrode GE and the source electrode SE for the TFT 3 of the type shown in FIG. 14A becomes larger, increasing the gate-source capacitance Cgs, while the facing area between the gate electrode GE and the source electrode SE for the TFT 3 of the type shown in FIG. 14B becomes smaller, decreasing the gate-source capacitance Cgs.
When the gate-source capacitance Cgs of the TFT 3 differs row by row, the value of .DELTA.V obtained from the equation (1) varies row by row. In the LCD device which uses the TFT panel shown in FIG. 9, the voltage holding characteristic of each pixel varies exposure area by exposure area, and varies row by row even in a single exposure area. When the same data signal is supplied to the individual pixels, the voltage held by each pixel varies exposure area by exposure area and row by row, causing display blurring.